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AMCC PPC440 开发板


       AMCC PPC440 是基于PowerPC的32bit RISC处理器

AMCC PPC440 内部框图

    ● Double data rate (DDR) synchronous DRAM (SDRAM) controller
          1.1GB peak data rate
           32-bit interface with optional ECC
           Eight-bit or wider devices
           DDR: 64, 128, 256MB; (4 bank devices)
          16MB to 256MB per bank , maximum 1GB total
           Supports discrete devices
           Page mode accesses w/bank interleaving
           Configurable paging (supports 8 open pages)
           Power management
           SSTL logic interface
    ● Peripheral component interconnect (PCI) bridge controller
           32-bit address/data bus, PCI v2.2 compatible (no 5V support)
           PCI bus frequency up to 66 MHz (asynchronous)
           Asynchronous clocking between PLB and PCI buses (optional)
           Supports 2:1, 3:1, and 4:1 clock ratios from PLB to PCI
           Power management and buffering
           Error tracking/status and PCI arbitration function
           PCI target-side configuration and processor access to all PCI address spaces
     ●Two Direct Memory Access (DMA) controllers
           DMA2P40 attached to 128-bit processor local bus
           DMA2P30 attached to 64-bit processor local bus
     ●Memory access layer (MAL) controller
           No restrictions on buffer alignment
           Aligned bus accesses to enable burst operation with external memories
           Configurable receive buffer size (configurable per channel)
           No minimum transmit buffer size
           Maximum buffer sizes of 4095 bytes (TX) and 4080 bytes (RX)
           Up to 256 descriptors in the buffer descriptor table per channel
           Configures EMAC according to commands specified in the descriptor status/control field
           Updates the descriptor status/control field at the end of packet transfer according to the status received from EMAC
           Buffer-based interrupt capabilities for each channel
           Concurrent operation of RX and TX channels
           Configuration using Device Control Registers (DCRs)
           Programmable PLB arbitration priority
           PLB/OPB error detection
     ●Z media independent interface (ZMII)
           Support for one MII PHY
           Support for two RMII PHYs
           Support for two SMII PHYs
           Programmable selection of any EMAC to drive MDI
           Programmable selection of any EMACto drive MII
           Programmable selection of either or both EMACs to drive RMII or SMII
     ●Two on-chip ethernet ports (EMAC0 and EMAC1)
           Multi-speed capability for full or half duplex at 10/100 Mbps
           2 KB transmit fifo, 4KB receive fifo
           One MII or two RMII/SMII ports
           Packet reject support
     ●General purpose timer (GPT)
           Provides a separate time base counter and system timers in addition to those defined in the processor core
           32-bit Time Base Counter driven by the OPB bus Clock
           Five 32-bit compare timers
    ● Two universal interrupt controllers (UICs)
           Supports programmable interrupt handling from a variety of sources
           Support for asynchronous level- or edge-sensitive interrupt types
           Programmable polarity for all interrupt types
           Support for 10 external and 64 internal interrupts
    ● Four universal asynchronous receiver/transmitters (UARTs)
           Compatible with the NS 16750
           16-byte send FIFO, 16-byte receive FIFO
           Full duplex operation
           Programmable baud rate generator
           Supports 5- to 8-bit word size, 1 or 2 stop bits, even, odd, or no parity
           1x 8-pin, or 2x 4-pin, or 1x 4-pin and 2x 2-pin, or 4x2-pin
    ● Serial peripheral interface (SPI)
           Full-duplex, synchronous, character-oriented (byte) port
           Allows exchange of data with other serial devices.
           4-wire serial port interface (receive, transmit, clock, and slave select)
           Each serial transaction transmits and receives one byte synchronous to the port clock provided by the master
           Programmable clock rate divider and clock inversion
           Up to 66 MHz OPB clock frequency
    ● Two inter-integrated circuit (IIC) controllers
           Complies with Phillips I2C specifications
           IIC0 supports an integrated bootstrap controller
           Two wire, bi-directional, open-drain, low-speed serial interface
           100-kHz and 400-kHz operation
           8-bit data transfers
           7-bit and 10-bit addressing
    ● General purpose I/O (GPIO) interface
           Allows flexible control of up to 64 multiplexed I/Os with user-defined functions
           Direct control of all functions from registers programmed via memory-mapped addresses
           Outputs can be programmed to emulate an open drain driver
    ● External bus controller (EBC)
           Provides direct attachment for most SRAM/Flash type memory and peripheral devices
           Minimizes the amount of external glue logic needed to communicate with memory and peripheral devices
           Supports device-paced transfers with optional bus-timeout
           Support for 8-bit and 16-bit masters
           Separate 30-bit address bus
    ● NAND Flash Controller
           Direct interfacing to discrete NAND Flash devices (up to 4 devices) or SmartMedia Card socket
           ECC generation: Hamming code, single bit correction, double bit detection (SEC/DED)
           x8 wide command write, x8 wide address write, x8 and x16 bit wide data read/write
           Automatically generates RE# and WE# strobes with configurable Strobe Pulse Width parameter
           Pin sharing interface to multiplex external data bus with external bus controller.
           Interrupt on device becoming Ready (after long page write or block erase operations).
           On-chip ROM controller:Alternate, extremely low latency boot source
           Interfaces to external bus controller to allow sharing of external I/O for data and chip select.
           Operates from a single externalbus controller peripheral clock.
           Clock gating for low power applications
    ● Universal serial bus (USB) interfaces
           USB 2.0 Device (UTMI), USB 1.1 Host (on-chip PHY), and USB 1.1 Device (on-chip PHY)"
           Provides a common solution for interconnecting various personal computer peripherals with a single host computing device.
           Half duplexed,packetized, single mastered, tiered treestructure, supporting up to 127 unique devices on the tree.
           Device ports support 6 independent endpoints (3 IN and 3 OUT), each 1024 bytes
           1024Byte FIFO (double buffering of 512Byte Packets)

       AMCC PPC440 Linux SDK 包括linux内核,全套的驱动源代码, 一些应用程序

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